Responsible for researching and developing image sensor pixel architecture and creating test strategies for leading edge complementary metal oxide semiconductor (CMOS) imaging technology. Responsible for studying and improving advanced pixel structures and developing imager architectures including periphery circuit design, simulation, layout, and timing implementation. Perform CMOS image sensor pixel development using TCAD simulation tool for advanced pixel architecture design. Optimizing the fabrication process to improve performance, which includes but not limited to signal-to-noise ratio (SNR), lag-free charge transfer, reduced dark current and hot pixels. Work with design, Process Integration Engineers, Process Engineers, Fab, and Color Filter Array (CFA)/microlens engineers to optimize pixel design and process for image performance. Engineering responsibilities includes the characterization of imager quantum efficiency, dark current, noise components, low light sensitivity, photon transfer curves, modulation transfer curves, lag and the correlation of this lab testing to the corresponding probe tests. Current products, next generation imager processes, competitor products and test structures will be characterized. Perform Special Work Requests (SWR) experiments on product, development, and test lots will be characterized. Develop a fundamental understanding of imager performance based on understanding of process, pixel layout, and electrical test conditions, and this will lead to the development of new characterization testing.